Memory devices, such as dynamic random access memories ("DRAMs"), are in common use in computer systems and a wide variety of other electronic products. To insure reliability, DRAMs, are thoroughly tested at several phases of the manufacturing process. For example, DRAMs are tested in die form, i.e., when they are still part of a wafer, and they are tested again after they have been packaged. The large volume of DRAMs that must be tested in a production environment necessitate that testing be performed utilizing automatic test equipment. However, to minimize the cost of testing and to maximize testing throughput, it is important to test DRAMs as quickly as possible. In the past, the rate at which DRAMs can be tested has been increased by compressing the data written to and read from DRAMs. Using data compression, data applied to the DRAM is written to several memory cells, either simultaneously or sequentially in a single memory access cycle. Compressed data is then read from the DRAM by simultaneously coupling data bits from several memory cells to a logic circuit that provides an indication of whether the data read from the memory cells corresponds to the data written to the memory cells. Data compression can markedly reduce the time required to test a DRAM, with the reduction being roughly proportional to the degree of compression. Data compression techniques have been used with a variety of DRAMs, including asynchronous DRAMs and synchronous DRAMs.
Recently, a high-speed packetized memory device, known as a RAMBUS DRAM or "RDRAM", has been proposed for use in computer systems. The interface to an RDRAM 10 is shown in the block diagram of FIG. 1. The RDRAM 10 is coupled to first and second 9-bit time-multiplexed data/address buses 12, 14. Each of the buses 12, 14 can couple either an address to the RDRAM 10 or data to or from the RDRAM 10. Within the RDRAM 10, the data/address buses 12, 14 are coupled to a multiplexer 16 that is controlled by appropriate circuitry (not shown) to couple any of the buses 12, 14 to the either an internal address bus 18 or an internal data bus 20.
The RDRAM 10 is also coupled to an 8-bit command bus RQ&lt;7:0&gt; that receives command packets for controlling the operation of the RDRAM 10. One of these lines, RQ&lt;0&gt;, receives a TestBSENSE signal during a core noise test described below. This TestBSENSE signal is coupled through two inverters 22a,b to provide an internal BSENSE_in signal and a row address latch RADR_L signal. The RADR_L signal is applied to a Row Address Latch Circuit 26 that latches a row address applied to the RDRAM 10. The BSENSE_in signal is applied to a Row Sense Control Circuit 28 that senses a row of memory cells corresponding to the latched row address.
Finally, the RDRAM 10 is coupled to a plurality of control and status lines, including a command "CMD" line, a serial clock "SCK" line, and a pair of serial input/output "SIO&lt;1:0&gt; lines. The SIO lines receive serial data on each transition of the serial clock SCK, such as such as control bits that are loaded into internal control registers, including a test option ("TO") register 24. The RDRAM 10 is, of course, also coupled to various power and ground lines, but these have been omitted for purposes of brevity.
It will be understood that the RDRAM 10 contains a large amount of circuitry in addition to the multiplexer 16 and the TO register 24. However, this other circuitry has been omitted in the interests of brevity and clarity since such circuitry is conventional in RDRAMs.
The RDRAM 10 illustrated in FIG. 1 includes internal circuitry specifically adapted to facilitate testing. One of these test modes, known as the "DA Mode", can be entered by setting a bit in a register either using the serial SIO port or issuing a command CMD through the command bus RQ&lt;0:7&gt;. Using these test modes, known data can be written to the RDRAM 10 and then read to verify the correct operation of the RDRAM 10 during production and thereafter. Another test, known as the core noise test, tests the RDRAM 10 under what may be considered "worst-case" conditions. In the core noise test, three events occur simultaneously, namely one of the memory banks (not shown) of the RDRAM 10 is precharged, data are written to or read from a memory location in the RDRAM 10, and a row of memory cells in a memory bank is "sensed," i.e., the memory cells are coupled to respective digit lines and their respective sense amplifiers respond thereto. Under these circumstances, it is possible for signals on various lines in the RDRAM 10 to be coupled to each other. The core noise test is selected by setting a core noise bit in the TO register 24 (FIG. 1) when it is programmed as described above. Once the TO register 24 has been programmed to perform a core noise test, the core noise option is alternately enabled and disabled by toggling the CMD signal line, which is coupled to the TO register 24.
In the DA test mode, the signals coupled to the lines and buses connected to the RDRAM 10 are given by the following table:
TABLE 1 DQA&lt;0&gt; DQ/Address DQA&lt;1&gt; DQ/Address DQA&lt;2&gt; DQ/Address DQA&lt;3&gt; DQ/Address DQA&lt;4&gt; DQ/Address DQA&lt;5&gt; DQ/Address DQA&lt;6&gt; DQ/Address DQA&lt;7&gt; DQ/Address DQA&lt;8&gt; DQ/Address DQB&lt;0&gt; DQ/Address DQB&lt;1&gt; DQ/Address DQB&lt;2&gt; DQ/Address DQB&lt;3&gt; DQ/Address DQB&lt;4&gt; DQ/Address DQB&lt;5&gt; DQ/Address DQB&lt;6&gt; DQ/Address DQB&lt;7&gt; DQ/Address DQB&lt;8&gt; DQ/Address RQ&lt;0&gt; TestBSENSE RQ&lt;1&gt; TestPRECH RQ&lt;2&gt; TestWRITE RQ&lt;3&gt; TestCOLLAT RQ&lt;4&gt; TestCOLCYC RQ&lt;5&gt; TestDSTB RQ&lt;6&gt; TestBLOCKD RQ&lt;7&gt; TestBLKSEL CFM TestCLKW CFMN VCC/2 CTM TestCLKR CTMN VCC/2 SCK SCK CMD CMD SIO&lt;0&gt; SIO&lt;0&gt; SIO&lt;1&gt; SIO&lt;1&gt;
The signal interface to the RDRAM 10 for the core noise test will now be explained with reference to the timing diagram of FIG. 2. Although many of the signals indicated above are used in various DA Mode tests, only the signals used in the DA Mode core noise test are illustrated in FIG. 2. Prior to time t.sub.1, a five-bit bank address PBSEL&lt;4:0&gt; is placed on one of the DQ/Address bus lines 11-16 . At time t.sub.1, the precharge signal TestPRECH applied to the RQ&lt;1&gt; line transitions high. The TestPRECH signal is a control signal that causes the RDRAM 10 to latch an address present on the DQ/Address bus lines 11-16 and precharge a bank of memory cells designated by the latched address. Thus, at time t.sub.1, the bank designated by the PBSEL&lt;4:0&gt; bank address is precharged.
Prior to time t.sub.2, a 5-bit bank address SBSEL&lt;4:0&gt; is again placed on lines 11-16 of the DQ/Address bus, and an 11-bit row address RADR&lt;10:0&gt; is again placed on lines 0-10 of the DQ/Address bus. The bank address SBSEL&lt;4:0&gt; and the row address RADR&lt;10:0&gt; correspond to a bank and row, respectively, of memory cells that are to be sensed. When the row of memory cells is sensed, each memory cell in the row is coupled to a respective digit line, a complementary pair of which is provided for each column, and a sense amplifier coupled to each complementary pair of digit lines responds thereto. Sensing a row is, of course, a precursor to reading data from selective columns of memory cells in that row
At time t.sub.2, a TestBSENSE signal applied to the RQ&lt;0&gt; line transitions low. The TestBSENSE signal is a control signal that causes the RDRAM 10 to latch a row and bank address present on lines 0-10 and 11-16, respectively, of the DQ/Address bus and sense a row of memory cells in the bank corresponding to the latched row and bank address. Thus, at time t.sub.2, the row designated by RADR&lt;10:0&gt; in the bank designated by SBSEL&lt;4:0&gt; is sensed.
At time t.sub.3, a TestBLKSEL signal applied to the RQ&lt;7&gt; line transitions high. As explained further below, when the TestBLKSEL signal is high, the function of the TestPRECH signal is altered.
At time t.sub.4, the core noise test is conducted. Prior to time t.sub.4, another bank address, CBSEL&lt;4:0&gt;, is placed on lines 11-16 of the DQ/address bus, and a column address CADR&lt;10:0&gt; is placed on lines 0-10 of the DQ/address bus. At time t.sub.4, a test column latch TestCOLLAT signal applied to the RQ&lt;3&gt; line transitions high. The TestCOLLAT signal causes the column address CADR&lt;10:0&gt; to be latched, and data signals to be coupled from or to the column designated by the latched column address. The data signals coupled from or to the column designated by the latched column address are in the row and bank that was previously sensed at time t.sub.2, as explained above. The RDRAM 10 thus reads data from or writes data to the column corresponding to the column address CADR&lt;10:0&gt; present at time t.sub.4 in the row and bank corresponding to the row address RADR&lt;10:0&gt; and bank address SBSEL&lt;4:0&gt; present at time t.sub.2.
At time t.sub.4, the TestBSENSE signal again transitions low. As explained above, when the TestBSENSE signal transitions low, a row designated by an address on lines 0-10 of the DQ/address bus in the bank designated by an address on lines 11-16 of the DQ/address bus is sensed. However, since it is necessary for the column address CADR&lt;10:0&gt; to be present on lines 0-10 of the DQ/address bus at time t.sub.4 to designate the column that is to be accessed in a read or a write, the column address CADR&lt;10:0&gt; is also used as the row address for sensing a row responsive to the transition of the TestBSENSE signal. Thus, at time t.sub.4, a row designated by the column address CADR&lt;10:0&gt; in the bank designated by the bank address CBSEL&lt;4:0&gt; present on lines 11-16 of the DQ/address bus at t.sub.4 is sensed. It is thus apparent that the row that is sensed during the core noise test must have the same address as the column that is accessed during the core noise test. This row/column dependency limits the flexibility in which the core noise test can be performed since it is not possible to independently select a row to be sensed when selecting a column to be accessed. Although this dependency is undesirable, there does not seem to be any solution because there are insufficient address lines to provide separate bank, row, and column addresses to the RDRAM 10 at the same time during the core noise test.
As mentioned above, the core noise test requires three events to occur at the same time. Sensing of a row and accessing a column of memory has been explained above. In addition, a bank of memory must also be precharged at us the same time. As explained above, banks of memory cells are precharged by the TestPRECH signal transitioning high, which then latches a bank address present on lines 11-16 of the DQ/address bus and precharges a bank corresponding to the latched address. However, as explained above, the address present on lines 11-16 of the DQ/address bus at time t.sub.4 corresponds to the bank to be sensed responsive to the TestBSENSE signal transitioning low. While this address could also theoretically be used to designate the bank to be precharged (in much the same manner that the column address at time t.sub.4 designates the row address), in practice it is not possible to both precharge and sense a bank. For this reason, the function of the TestPRECH signal is altered responsive to the TestBLKSEL signal on the RQ&lt;7&gt; control line transitioning high at time t.sub.3, as alluded to above. Thereafter, the TestPRECH signal is still used to precharge a bank, but it does not precharge the bank designated by an address present on lines 11-16 of the DQ/address bus. Instead, the transition of the TestPRECH signal precharges a bank corresponding to 1 bank higher then the bank most recently precharged. Thus, the bank that is precharged at time t.sub.4 responsive to the TestPRECH signal is one bank higher than the bank precharged at time t.sub.1. For example, if bank 14 was precharged at time t.sub.1, then bank 15 will be precharged at time t.sub.4 during the core noise test.
It will be noted that 17 of the 18 lines of the DQ/address buses 12, 14 are used to provide addresses during the core noise test. For this reason, data coupled to or from the RDRAM 10 must be time-multiplexed with the addresses present on the DQ/address lines. The inability to couple data to or from the RDRAM 10 at the same time that addresses are coupled to the RDRAM 10 increases the time needed to test RDRAMs 10. While it would be desirable to couple data to or from RDRAMs 10 at the same time that they are addressed, this does not seem to be possible since there are not even enough DQ/address lines to eliminate the row/column dependency described above.
The inability to either solve the row/column dependency problem or allow coupling of data to or from RDRAMs at the same time that they are addressed would be exacerbated by any attempt to reduce the number of lines that are used to couple signals to or from RDRAMs 10 during the core noise test. However, it is desirable to minimize the number of signal lines that must be used during testing for several reasons. For example, automatic test equipment used to test DRAMs having fewer number of signal lines than RDRAMs might be incapable of testing RDRAMs. Such automatic test equipment, which is very expensive, would then be obsolete. It would be desirable to be able to use older automatic test equipment to test RDRAMs. However, doing so, even if it were possible, would appear to only exacerbate the row/column dependency problem and the need to multiplex data and address signals.
There is therefore a need to be able to more efficiently test RDRAMs by reducing the number of connections that must be made to RDRAMs during core noise testing without requiring the multiplexing of data and address signals and without making the row to which a read or write accesses occurs being dependent on the column that is accessed.